This application claims benefit of priority under 35 USC 119 based on Japanese patent application PH11-371736 filed Dec. 27, 1999, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to an emulator and a method of emulation for using testing a system having complex interfaces such as RAMBUS interface or DRAM interface.
2. Description of Related Art
System LSIs (Large Scale Integration) and microprocessors are directed much research to method of so-called system on-chip. High-speed and low amplitude memory interfaces such as RAMBUS I/F (Interface) or DRAM I/F have become the de-facto standard for memory interfaces.
FIG. 1 illustrates a system chip having a RAMBUS I/F and a DRAM I/F. In FIG. 1, this system chip 100 comprises a CPU 101 connected to a system bus 102, a RAMBUS I/F 103, and a DRAM I/F 104 connected to the system bus 102. The RAMBUS I/F 103 and DRAM I/F 104 are connected to a tester 105. The tester 105 outputs and inputs data to/from the system chip 100 via these I/Fs.
In such case, it becomes very difficult to test under the regulation frequency employing conventional tester since the system chip having complex interfaces such as the RAMBUS I/F 103 or DRAM I/F 104 is getting more complex, i.e. higher transfer speed and lower amplitude. On the other hand, the stable testing could not be realized even if the test could carry out. Or these tests need to be employed a high-performance, expensive and inflexible tester.
FIG. 2 illustrates a system chip having a scan register 112. In FIG. 2, the scan register 112 is used for scanning the internal status of the system chip 110. The scan register 112 is provided between the system bus 113 and the CPU 111 to store the test vector and the result. To examine the internal status of the system chip 110, the system chip 110 had to be suspended, and then the stored test results in the scan register 112 are shifted to the tester 115 via RAMBUS 115.
The test using the scan register may cause failure since the system chip has special I/Fs like RAMBUS I/F as mentioned above. And it is impossible to test depending on operation frequency of the system chip since the system chip must be suspended.
The present invention is to provide an emulator and a method of emulation for using testing a system having complex interfaces capable of stable testing can be realize under the system regulation frequency or less frequency without using the high-performance and expensive tester.
The emulator of this invention comprises a content addressable memory (CAM) configured to store addresses accessed by a system to be tested, a memory unit having storage area corresponding to the entry of the CAM, configured to store data corresponding to the address stored in the CAM and test information for emulation, a shift register configured to store data and test information from a tester and transfer the data and the test information to the CAM and the memory unit, and a state machine configured to receive a request from a system or a tester and control transferring between a system and a tester.